IBM has announced the production of 5-nanometer chips based on a new standard that will say goodbye to the FinFET standard. The process uses a new structure with a stack of four nanoplates to fit 30 billion transistors on a chip the size of a knuckle. This means that extremely powerful chips will be produced in very small dimensions in terms of processing. Minimizing lithography always means higher productivity and lower power consumption in the same architecture, and with IBM’s new technology, it is possible to keep power consumption low by increasing processing power.
Moore’s Law, which was first proposed in the 1970s, stated that the number of transistors on a chip would double every two years. But in recent years, this law has been challenged by the physical limitations of silicon, slowing the rate of transistor additions. Currently, 14-nanometer chips are widely used in the consumer electronics market. However, Intel and Samsung have switched to 10-nanometer chips to stay ahead of their competitors.